1. Field of the Invention
The present invention relates generally to semiconductor package technology and, more particularly, to an integrated circuit chip package having a decoupling capacitor disposed therein so as to reduce simultaneous switching noise.
2. Description of the Related Art
The rapid and continuing advances in integrated circuit (IC) technology have resulted in many new challenges to the interconnection package design. The number of devices that has been integrated on a single chip is dramatically increased, while the devices are becoming more sensitive to the power-ground noise.
When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. Simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN). The simultaneous switching noise can cause logic circuits to switch state falsely, and signal/power integrity issues have significant impacts on the performance of high-speed systems. The simultaneous switching can also cause problems in signal timing and quality such as signal degradation in rise time, signal channel transmission delay skew, and an increase in signal overshoot.
Use of a decoupling capacitor is one known technique of reducing the effects of undesirable simultaneous switching noise. Normally, the decoupling capacitor is mounted on a motherboard in the form of a discrete component, while being apart from the (IC) chip package. However, in high-speed, high-frequency systems, the decoupling capacitor is disposed within the IC chip package so as to reduce parasitic parameters caused by longer connection paths, thereby to improve electrical performance.
FIG. 1 shows, in a plan view, an internal structure of a conventional IC chip package 10 in which a decoupling capacitor 13 is disposed. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.
Referring to FIGS. 1 and 2, the package 10 has an IC chip 12 and the decoupling capacitor 13 attached side by side onto a circuit substrate 11. The decoupling capacitor 13 is electrically coupled to the IC chip 12 and to the circuit substrate 11 via bonding wires 14. A power/ground ring 15 is formed on the circuit substrate 11, surrounding the IC chip 12. The power/ground ring 15 is used to electrically connect, or merge a, number of power/ground pins. Although other bonding wires typically are formed to directly connect signal pins between the IC chip 12 and the circuit substrate 11, they are not depicted in the drawings for clarity of illustration.
Typically, the conventional package 10 may use a bulk capacitor, e.g. the decoupling capacitor 13, which is, for example, about 1 mm, 1 m, and 2 mm in width, length, and height, respectively. Thus, the bulk capacitor 13 occupies excessive internal space in the package 10, leading to increases in size of the package 10, especially its thickness or height. Furthermore, the conventional decoupling capacitor 13 is coupled to a single kind of power pins, so several capacitors 13 are needed depending on the kinds of power pins. Moreover, the mounting position of the capacitor 13 on the substrate is restricted according to that of the power/ground pins of the IC chip 12.
As described above, the conventional decoupling capacitor 13 uses the bonding wires 14 for electrical connections to both the IC chip 12 and the circuit substrate 11, thereby requiring double wire bonding. In addition, the capacitor 13 typically is greater than the IC chip 12 in height, so the bonding wires 14 coupled to the capacitor 13 increase in length and undesirable inductance. Also, the bonding wires 14 made of gold have a greater resonance peak causing the troublesome simultaneous switching noise.